There are two separate NVICs (interrupt controllers) - the NVIC is part of the CortexM0+ core, and the RP2040 has two of them.[*]I guess I need to do some more reading to understand the overall interrupt mechanisms better. I'm not yet clear on how even though there's the singular vector table shared by both cores, the doorbell IRQ only triggers on the core which receives the doorbell (don't get me wrong, that's what I'd hope would happen, just haven't completely wrapped my head around how it works)
They could in principle have completely different interrupts on the two cores (ie. the NVIC inputs wired arbitrarily), but in fact in the RP2040 design almost all the interrupt sources are wired in parallel to the same NVIC inputs on both cores.
The vector table is just a piece of ordinary memory (normally RAM, but nothing stopping it being in flash apart from the poor performance). The NVIC has a register pointing to the vector table (VTOR), and the Pico SDK happens to set that register to the same value in both cores. The vector table is just a list of addresses of the interrupt handlers, so there's no magic in it being shared or not.
For inter-core communication, it's common to use the inter-core FIFOs, and the interrupts from these are split so you can have a separate handler for each end (see 2.3.1.4 in the datasheet).
You originally mentioned "Pico", so I've answered this in respect of RP2040, but your mention of Doorbells now makes me think you are talking about Pico2/RP2350. The interrupt arrangements there are very similar, but don't have the paired interrupts for the inter-core FIFOs (they are separate, but wired to the same interrupt number on each core, so need separate vector tables to take advantage).
Statistics: Posted by arg001 — Fri Jan 03, 2025 10:27 pm