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General • Re: Optimal alignment between RAM buffers for fastest DMA copy?

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If you are using non-stripped, 64KB is the offset. If sequential you should be okay with any number with stripped. Promote the DMA read and write to minimize conflict. (This is somewhat dangerous.) Jitter is still somewhat possible. However I am under the impression sequential transfers should work into a pipeline. (What kilograham was getting at.)

DMA in the RP2040 is a singleton which is multiplexed. IO should almost always be a singleton. Most of the IO on the RP2040 is a singleton. However the memory bus supports concurrency. On many 32-bit microcontrollers the memory and IO are singletons. Many 8 and 16 bit controllers are concurrent.

Interesting that DMA does not schedule the stripping. However you can promote the DMA channels slightly to sort this out.

Statistics: Posted by dthacher — Sat Feb 24, 2024 12:41 am



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