It's not really clear to me what the word its refers to in this sentence: "This is because the slave select pin freezes the data in its serial peripheral register and does not permit it to be altered if the SPH bit is logic zero." I guess it is talking about the slave SPI. If you configure the master and slave(s) for SPH=1, then "For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive data words...", so maybe that's an option for you. E.g.:For the master side, when running with SPO=1, SPH=0, I omit this:and then manually control the CSn GPIO(s). I can hold CSn low for continuous back-to-back transfers when the SPI slave is an SD card, for example.
Code:
spi_set_format(spi_p->hw_inst, 8, SPI_CPOL_1, SPI_CPHA_1, SPI_MSB_FIRST);Code:
gpio_set_function(PICO_DEFAULT_SPI_CSN_PIN, GPIO_FUNC_SPI);Statistics: Posted by carlk3 — Wed Sep 04, 2024 5:40 am