General • RP2350 RISC-V qustions

The RISC-V implementation is clever.
Is that a unique approach?

Maybe. AIUI you can run one RISCV and one Arm core in parallel, on the same memory bus, which is pretty unusual.

Interesting.
So you always boot with 2 CPUs active, either M33+M33 or V+V or M33+V?

All features of the chip, apart from a handful of security features, and the double-precision floating-point accelerator, are available in RISC-V mode.

If only looking at integer performance without floating point computations, and since M33 and RISC-V are both running at 150MHz, which is better is decided by the compiler output generated for M33 or RISC-V. Did you do any testing regarding integer performance of M33 vs. Hazard3 on the RP2350?

Statistics: Posted by HermannSW — Tue Aug 13, 2024 11:12 pm