Sorry I know there's many posts similar to this. The ones I read all seemed to have clear schematic issues, much worse routing, or no information. Perhaps a pinned megathread could encapsulate connectivity issues? The RP2040 seems particularly finnicky so having them all in one place would be awesome.Please don't start a new thread each time.
The probe used was a Tektronix P6245, so <= 1pF.By low capacitance probe how low ? 1pF ? thats 10% of the load capacitor. 12.000250MHz is +21ppm. So without probe load its even higher. The best way to measure a crystal frequency is either to output the clock on another pin, or just use a probe near but not connected to the crystal and a spectrum analyser.
Given I have gotten this device to work with clocks well away from 12MHz (several thousand PPM off), I am not too worried about deviations <100ppm. I believe the crystal is healthy at this time.
Thank you for pointing out the SPI lines, I hadn't put much thought into those, but it would make sense if the firmware is not being stored/read properly due to SI issues. I will probe that bus and see if there's any funny business happening.I'm not sure from the plots I can understand the reference planes for all the signals. Each signal needs an adjacent return paths. It looks as though the flash signals are reference to the VCC plane a ground plane would be more conventional
Try adding a 100R resistor on the SPI clock to ground on the bottom of the board under the flash chip incase the there is signal integrity issue.
You are correct that these lines are referenced to a VCC plane on the bottom layer, and actually cross a 3V3/GND plane boundary on Layer 2. Not ideal.
Fair point, there are two bypass caps which I couldn't get ideal placement for. One of them out of fear of interference with a mounting screw. I avoided via-in-pad for any 0201 components for reliability concerns. In future iterations I think I will limit myself to 0402 minimum as working with 0201 is a total PITA during debug. It would be shocking if those two bypass caps are a major source of problems, but good to check everything.Some of the decoupling capacitor don't appear to have a very small loop area. If layer 2 was a solid ground plane that would help and if the ground side of each decoupling capacitor had its own ground connection to the ground plane that would be good. You have use via in pad , I'd suggest that you do that for all the decoupling capacitors.
I've acquired a can of freeze spray. I'll try isolating which component starts working at low temps & will report back when time allows.
Thanks for the suggestions!
Statistics: Posted by MMI_Modular — Thu Jul 25, 2024 8:07 pm