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Interfacing (DSI, CSI, I2C, etc.) • Re: DSI bug on Pi 5

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Thanks for reporting this -- the RP1 DSI driver has not had a lot of testing on panels other than our standard ones, and could well have holes and bugs which we will hopefully fix...

Yes your assumption is correct; the other changes on that PR are mostly to do with 4-lane operation (specifically, when 8*lanes > bpp) and shouldn't make a difference. The relevant change is the better calculation for DSI_TO_CNT_CFG. Setting it to zero (no timeout) also helps but there's no need for both.

Now my (untested) guess is that this is related to MIPI_DSI_MODE_VIDEO_BURST, which I believe the vc4 driver ignores.

Statistics: Posted by njh — Wed Jul 03, 2024 2:52 pm



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