Eliminating Q6 (the transistor) seems to be enough to overcome our immediate problem.
Is there any guidance on the SYNC pins? We're interested in actually using the hardware PTP clock in the future.
Our FPGAs inputs provide weak pullups at least until startup is finished (and currently at all times because the pins are unused), we could counter that with stronger pulldowns if power sequencing requirements make that necessary.
Greetings, Martin
Is there any guidance on the SYNC pins? We're interested in actually using the hardware PTP clock in the future.
Our FPGAs inputs provide weak pullups at least until startup is finished (and currently at all times because the pins are unused), we could counter that with stronger pulldowns if power sequencing requirements make that necessary.
Greetings, Martin
Statistics: Posted by martinb42 — Tue Jun 18, 2024 12:04 pm