1. The code is running at EL1, but you have to configure CNTHCTL_EL2 to allow accessing the CNTP* registers before dropping to EL1.
The following are all my EL2 register configurations after a cold reset just in case you're missing something else:
2. My example handles IRQs synchronously and cooperatively because it's for a non-real-time bare metal application; the exception vector table is configured to keep IRQ and FIQ exceptions masked on return, so I don't get any more IRQ or FIQ exceptions until I'm done handling all IRQs and put the CPU to sleep. If you're building a kernel that is preemptive even in kernel code, you will have to expose some form of locking that also masks interrupt exceptions to prevent context switches while executing non-reentrant code, which makes things much harder. You can, however, build a kernel that does cooperative multitasking in kernel code and preemptive multitasking in user code, in which case you can follow my approach.
3. Your code seems to be almost correct. The spurious 1023 IRQ is the interrupt controller telling you that there are no more IRQs left to handle, so you can unmask IRQ and FIQ exceptions in PSTATE by clearing the I and F bits from DAIF and put the CPU to sleep. If you put the CPU to sleep without unmasking interrupt exceptions it will sleep forever.
The following are all my EL2 register configurations after a cold reset just in case you're missing something else:
Code:
// Set up EL2 registers. adr x0, ivec msr vbar_el2, x0 mov x0, #0x8000 << 16 msr hcr_el2, x0 mov x0, #0x30cd << 16 movk x0, #0x830 msr sctlr_el2, x0 mov x0, #0x30 << 16 msr cptr_el2, x0 mov x0, #0x3 msr cnthctl_el2, x0 mrs x0, midr_el1 msr vpidr_el2, x0 mrs x0, mpidr_el1 msr vmpidr_el2, x0 mov x0, #0xc4 msr spsr_el2, x0 adr x0, start msr elr_el2, x03. Your code seems to be almost correct. The spurious 1023 IRQ is the interrupt controller telling you that there are no more IRQs left to handle, so you can unmask IRQ and FIQ exceptions in PSTATE by clearing the I and F bits from DAIF and put the CPU to sleep. If you put the CPU to sleep without unmasking interrupt exceptions it will sleep forever.
Statistics: Posted by Fridux — Mon Jun 10, 2024 10:57 am